Ben Eater’s 8 Bit Computer (SAP-1) in an FPGA: The ALU

This is the second video in a series of videos on implementing Ben Eater’s 8 Bit Computer in an FPGA.

Ben Eater’s 8 Bit Computer is actually based on a computer called the SAP-1 from the book “Digital Computer Electronics” by Paul Malvino and Jerald Brown.

In this second video, we will implement the Arithmetic Logic Unit or ALU module in a hardware definition language called Verilog. We can use the ALU module to implement all of the mathematical functions in the SAP-1 computer including addition and subtraction.

Later in this video series, we will add multiplication and division as well as some other logic functions in our ALU. Once we have completed implementing the SAP-1/Ben Eater 8-bit computer architecture, we will expand this design with more memory, more CPU instructions, and we will even be creating an assembler for our expanded computer!

I hope this video will be educational and entertaining and maybe you will learn some Verilog and FPGA design along the way via a practical example.

The first video in this series can be found here:

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